1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device used for a dynamic RAM.
2. Description of the Related Art
A structure of this type of conventional semiconductor memory device is illustrated in FIGS. 4A and 4B. FIG. 4A shows a pattern of the semiconductor memory device, and FIG. 4B a sectional view taken on line A--A of FIG. 4A. Reference numeral 1 designates a p-type semiconductor substrate; 2 a field insulating film; 3 a channel stop impurity layer, 4, 10, and 11 n-type impurity layers; 5 a capacitor insulating film; 6 capacitor electrodes; 7 an interlayer insulating film; 8 a gate insulating film; 9 word lines; and 13 data lines.
Referring to FIG. 4B, a potential applied to the data line 13 is applied to the drain 11 of each transfer transistor whose gate electrode is the word line 9 associated with it. When the potential of the word line 9 is raised, the conductivity of the portion of the substrate directly under the gate insulating film 8 is inverted as a result, data is transferred to the source 10 of the transfer transistor. The source 10 connects to the storage node 4. Charges are stored in a metal insulator semiconductor (MIS) capacitor element, which is formed between the storage node and the capacitor electrode 6. The capacitor insulating film 5 is interlaid between the node and the capacitor electrode.
In the above prior art semiconductor memory device, the memory cells are arrayed two-dimensionally on the major surface of the semiconductor substrate 1. An approach to the 3-dimensional structure has been made. For example, as shown in FIG. 4B, the substrate 1 is trenched. However, so long as the cells are arrayed two dimensionally, the number of cells allowed to be carried on a given chip is limited. In this respect, it cannot be expected that an integration density of the chip is greatly improved.